1. Field of the Invention
The invention relates to semiconductor fabrication, and in particular the design of a critical dimension test structure for measuring the change in dimensions of elements on the surface of a semiconductor integrated circuit during processing.
2. Description of the Prior Art
Most semiconductor devices are now made by photolithographic techniques. Such techniques involve the exposure of the surface, coated with light-sensitive material, of a semiconductor body to a particular pattern, and the subsequent formation or development of that pattern into permanent form through the use of wet or dry etching techniques that create various regions and structures on the surface of the semiconductor body. As is well known in the art, photolithographics procedures require that masks be used to define those portions of the semiconductor material where various portions of the semiconductor devices are to be located. Because different parts of these semiconductor devices must be located at precisely defined distances from one another, it is necessary that not only each of the masks be used in forming the semiconductor devices be precisely aligned with respect to one another, but also that each fabrication step which forms or develops one of the regions to a specific dimension also be highly precisely defined both in vertical and horizontal direction.
In many cases, the determination of the pattern determining the fidelity is done by an operation examining the surface of the semiconductor wafer under an optical line width measurement equipment. The use of marks on the mask and the wafer are known to facilitate the dimensional measurement procedure. However, prior to the present invention scale marks were not of use in dimension monitoring to determine the extent of formation or development of particular critical areas of the device in terms of the change in dimensions of lines or areas in response to wet or dry development or etching.